The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still...

In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there ...

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Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. ...

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors en...

An accurate and e cient method for modelling CMOS gates by a single equivalent transistor is introduced in this paper. The output waveform of a CMOS inverter is obtained by solving the circuit di€ erential equation considering only the conducting transistor of the inverter. The e€ ect of the short-circuiting transistor is incorporated as a di€ erentiation of the width of the conducting transis...

This paper presents a compact programmable biphasic stimulator for cochlear implants. By employing double-loop negative feedback, the output impedance of the current generator is increased, while maximizing the voltage compliance of the output transistor. To make the stimulator circuit compact, the stimulation current is set by scaling a reference current using a two stage binary-weighted trans...

An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a...