Software testability took a lot of interests of software community. Indeed, this concept has been interpreted in a variety of ways. One interpretation is concerned with the extent of the modifications a program component requires, so that the entire behavior of the component is observable and controllable. Another interpretation is the ease with which faults, if present in a program, can be rev...

This paper compares the dynamic testability prediction technique termed "sensitivity analysis" to the static testability technique termed cyclomatic complexity. The application that we chose in this empirical study is a CASE generated version of a B-737 autoland and yawdamp systems. For the B-737 systems we analyzed, we isolated those functions that we predict are more prone to hide errors duri...

We introduce the hemicubic codes, a family of quantum codes obtained by associating qubits with $p$-faces $n$-cube (for $n>p$) and stabilizer constraints faces dimension $(p\pm1)$. The code identifying antipodal resulting complex encodes one logical qubit into $N = 2^{n-p-1} \tbinom{n}{p}$ physical displays local testability soundness $\Omega(1/\log(N))$ beating current state-of-the-art $1/\log...

An analysis is given and proposals are presented to improve the maintenance level in implementation of law 297-FZ, Art. 11 by improving testability suitability for diagnostics resource-determining nodes domestic energy-saturated equipment

Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-fle...

On-line testability is essential in designs with high reliability requirements. High-level synthesis reduces time-to-market and enables efficient design space exploration. In our work, we implement on-line testable designs in a high-level synthesis environment. We refer to our new technique (inversion testing) and exploit its features, in an attempt to reduce hardware penalties. Further, we enh...