This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

A manned submersible was used in a fjord in southeastern Alaska to study the distributional patterns of the red king crab (Paralithodes camtschaticus) and the Tanner crab (Chionoecetes bairdi) in summer. The cove was divided into three zones: inner, middle, and outer. Six types of habitats, including sand-mud, rock, shell, debris, rock wall, and algae, were identified from video tapes. A relati...

A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF are introducing in this paper. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pulldown transistors. The aim of the DDFF-ELM is to ...

This paper proposes a new design of 2T AND gate. Performance comparison of proposed gate with existing 2T GDI technique is presented. Different methods have been compared with respect to the number of devices, power consumption, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing 2T gate design. The simulation has...

Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It o...

In most of the digital systems the full-adders are the basic and the fundamental components. Due to the increase in number of transistors on the chip and its shrinkage has made the power consumption to be more. This power consumption is due to the flow of current and causes the battery life to be reduced. Hence the need of low power designs is the primary requirement in the VLSI field. The full...

2-bit magnitude comparator design using different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison between different logic styles used to design 2-Bit magnitude com...

We present two sequences of ensembles of non-systematic irregular repeat-accumulate codes which asymptotically (as their block length tends to infinity) achieve capacity on the binary erasure channel (BEC) with bounded complexity per information bit. This is in contrast to all previous constructions of capacity-achieving sequences of ensembles whose complexity grows at least like the log of the...

OBJECTIVES To estimate age at attaining Tanner stages in Ugandan/Zimbabwean HIV-infected children initiating antiretroviral therapy (ART) in older childhood and investigate predictors of delayed puberty, particularly age at ART initiation. DESIGN Observational analysis within a randomized trial. METHODS Tanner staging was assessed every 24 weeks from 10 years of age, menarche every 12 weeks...