 Traditional 2-level high-frequency pulse width modulation (PWM) inverters for motor drives have several problems associated with their high frequency switching which produces common-mode voltage and high voltage change (dV/dt) rates to the motor windings. Multilevel inverters solve these problems because their devices can switch at a much lower frequency. Two different multilevel topologies a...

Main flux saturation in induction machines plays an important role in a number of operating regimes and therefore has to be accounted for in the process of modelling. The current state space model of a saturated induction machine has gained substantial popularity recently as an excellent tool for transient and steady-state time domain analysis of induction motor drives when the main flux satura...

 Traditional high-frequency pulse width modulation (PWM) inverters for motor drives have several problems associated with their high frequency switching which produces high voltage change (dV/dt) rates. Multilevel inverters solve these problems because their devices switch at the fundamental frequency. Two different multilevel topologies are identified for use as a converter for electric drive...

This paper presents a cost-effective vector control strategy for four switch three phase (FSTP) inverter fed a synchronous reluctance motor with conventional rotor (SynRM) drive. The reduction of the number of power switches from six to four improves the cost-effectiveness, volume-compactness and reliability of the three phase inverters. In this paper, a simulation model of the drive system is ...

This paper presents the control approach for single inverter dual coupled brushless DC motors (DCBLDC) drive system. One of the basic requirements of such systems, is the power balance between two motors and on the other hand, minimizing mechanical fluctuations in order to avoid mechanical equipment damage especially in the state of mechanical resonance. This paper also presents an improved for...

In all multilevel topology with several DC link, the voltage balancing problem of DC capacitors is a key problem. This paper proposes a new topology of chopper circuit for dc capacitor voltage balancing in diode clamped multilevel inverters (DCMLI). In the presented topology the number of switches is reduced respect to other proposed topology in literatures. Suggested topology is modular and ha...

This paper proposes two methods to improve the performance in real-time simulation. The increased inverter-based generations are gradually shifting operation of power grid. Consequently, investigation for safe and further application is essential inverter-dominated As simulated number non-linear switch elements like inverter increases, numerical complexity simulation model rises exponentially. ...

This paper proposes fluorescent electronic ballast with high power factor and low line input current harmonics. The system performance can be improved by a charged pump circuit. Details of design and circuit operation are described. The proposed electronic ballast is modified from single stage half bridge class D electronic ballast by adding capacitor parallel with each power switch and setting...

In the viewpoint of reliability implication and cost effectiveness of three phase inverter, there should be less device count in inverter topology and fewer losses in the semiconductor switches. The earlier reported less device count topology by many research groups are facing the problem of Total Harmonic Distortion (THD). The imperfect design value of DC link capacitor is the main reason of H...

Multilevel Inverters have emerged in power conversion systems due to their lower output harmonics and high power capability. This paper presents the performance analysis of a new seven level symmetrical multilevel inverter with reduced number of switches using Carrier Overlapping PWM strategies. Due to switch combination redundancies, there are certain degrees of freedom to generate multilevel ...