نتایج جستجو برای: stack 3

تعداد نتایج: 1825912  

2005
BRIAN CONRAD

Suppose X is a locally noetherian Deligne–Mumford stack. Definition 1.2 has an obvious variant X̂ét using the underlying smaller étale site Xét and the restriction Oc Xét of Oc X to this site. By [3, 12.7.4], the category of cartesian Oc X -modules on Xlis-ét is equivalent to the category of Oc Xét-modules on Xét: (1.1) ModXlis-ét,cart(Oc X ) ' ModXét(Oc Xét) Definition 1.3. Let X be a locally n...

1995
Joseph L. Ganley

A Halin graph the union of a tree with no degree-2 vertices and a cycle on the leaves of the tree. This paper examines the problem of laying out Halin graphs using stacks and queues. A k-stack (k-queue) layout of a graph consists of a linear ordering of the vertices along with an assignment of each edge to one of k stacks (queues). The ordering and the edge assignments must be made such that if...

2006
Huibin Shi

Today, many general-purpose register-file (GPRF) architectures implement instructionlevel-parallelism (ILP) techniques to improve performance. Less has been done in this area for the so-called ‘stack architecture’. Nonetheless, stack architectures have many advantages over GPRF architectures. Applying ILP techniques in the stack processor domain might ultimately achieve similar, or better, perf...

Journal: :Nature Electronics 2020

Journal: :Nature 2016

Journal: :Prikladnaya diskretnaya matematika. Prilozhenie 2018

2002
Ryan Rakvic Ed Grochowski Bryan Black Murali Annavaram Trung Diep John P. Shen

The Intel® ItaniumTM architecture provides a virtual register stack of unlimited size for use by software. New virtual registers are allocated on a procedure call and deallocated on return. Itanium processors implement the register stack by means of a large physical register file, a mapping from virtual to physical registers, and a Register Stack Engine (RSE) that saves and restores the content...

2004
Jun-Cheol Park Vincent John Mooney Philipp Pfeiffenberger

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design. Our sleepy stack approach retains exact logic state – making it...

Journal: :Optics letters 2012
Ling Lu Lin Lee Cheong Henry I Smith Steven G Johnson John D Joannopoulos Marin Soljačić

We designed and analyzed a "mesh-stack" three-dimensional photonic crystal of a 12.4% bandgap with a dielectric constant ratio of 12 : 1. The mesh-stack consists of four offset identical square-lattice air-hole patterned membranes in each vertical period that is equal to the in-plane period of the square lattice. This design is fully compatible with the membrane-stacking fabrication method, whi...

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