This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 500C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the e...

Embedded SRAM is involved in many low-energy applications, e.g. stand-alone wireless sensor nodes. SRAMs have the highest energy contribution in such applications. Unlike dynamic RAM, it does not need to refresh. In modern Trends, the demand for memory has been increases tremendously. We analyze Schmitt-Trigger (ST)-based static random access memory (SRAM) bitcells for ultralow-voltage operatio...

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control wi...

This paper presents the different types of analysis such as noise, voltage, read margin and write margin of Static Random Access Memory (SRAM) cell for high-speed application. The design is based upon the 0.18 μm CMOS process technology. Static Noise Margin (SNM) is the most important parameter for memory design. SNM, which affects both read and write margin, is related to the threshold voltage...

As the standby supply voltage for the static RAM (SRAM) design scales down for the low-power purpose, the static noise margin of SRAM also decreases. If the supply voltage is below the data retention voltage (DRV), the data need to be checked and corrected before they are sent out of the memory block. In this project, we study the effect of implemented error correction code (ECC) technique to t...

SRAM-based FPGAs are increasingly becoming more popular in applications where high dependability, low cost, and fast time-tomarket are important constraints. However, these devices are more susceptible to single-event upsets (SEUs) compared ASIC designs. The error models of SRAM-based due to SEUs are more complicated than those of ASICs since soft-errors in the configuration memory result in pe...

The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potent...

Ternary content-addressable memory (TCAM) is often used in high speed search intensive applications such as ATM switch, IP filters. Hence, currently ZTCAM, is introduced which emulates the TCAM functionality with SRAM. It has some drawbacks such as low scalability, low storage density, slow access time and high cost. But this paper proposes novel memory architecture of existing Z-TCAM, but with...

Our present research endeavor focuses on the factors of hybrid single electron transistor (SET)-CMOS based static random access memory (SRAM). Ultra small low power dissipated SET is combined with high gain and high current drivable CMOS and the write operation of the memory cell is briefly analyzed. This work is a comparative work of power consumption between conventional CMOS based SRAM and h...

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the are...