The construction of China’s high-speed rail has been arousing controversy for the possibility exacerbating regional imbalance. This paper provides an empirical analysis based on panel data 276 prefecture-level cities during 2007–2018 to explore authenticity this inference. threshold model is adopted investigate whether economic growth becomes stronger and more equal among under impact rapidly e...

Promoting the seed regeneration potential of secondary forests undergoing gap disturbances is an important approach for achieving forest restoration and sustainable management. Seedling recruitment from seed banks strongly determines the seed regeneration potential, but the process is poorly understood in the gaps of secondary forests. The objectives of the present study were to evaluate the ef...

By using staggering magnets, we obtain a particular type of magneting bearings, owning very interesting properties : plane gap, null axial force, and absence of coupling produced by magnetization non-homogeneities. These bearings are well adapted for low rotational speed systems, and for partially-magnetic suspensions.

The RAMpage memory hierarchy is an alternative memory organization which addresses the growing CPU-DRAM speed gap, by replacing the lowest-level cache by an SRAM main memory. This paper presents some modifications to the RAMpage hierarchy. More aggressive first level cache implementations are shown to improve performance of the RAMpage model, when context switches were taken on misses to DRAM.

Processor speed is increasing at a very fast rate comparing to the access latency of the main memory. The effect of this gap can be reduced by using cache memory in an efficient manner. This paper will discuss how to improve the performance of cache based on miss rate, hit rates, latency, efficiency, and cost. Keywords—Cache optimization; cache miss; latency; memory

The current practice of specifying simultaneous gap out logic at isolated high speed signalized intersections places constraints on the signal controller logic that cannot be satisfied under high congestion level. Further, it often results in degraded signal efficiency and dilemma zone protection. A stochastic approach is proposed in this paper with the objective of increasing safety and effici...

To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. In this paper, a new architecture, QUKU, is described which uses a coarse-grained reconfigurable PE array (CGRA) overlaid on an FPGA. The low-speed reconfigurability of the FPGA is used to optimize the CGRA for different applications, whilst the high-speed CGRA ...

This article presents two systolic architectures to speed up the computation of modular multiplication in RSA cryptosystems. In the double-layer architecture, the main operation of Montgomery's algorithm is partitioned into two parallel operations after using the precomputation of the quotient bit. In the non-interlaced architecture, we eliminate the one-clock-cycle gap between iterations by pa...

Improvements in the processing speed of multipro cessors are outpacing improvements in the speed of disk hardware Parallel disk I O subsystems have been proposed as one way to close the gap between proces sor and disk speeds In a previous paper we showed that prefetching and caching have the potential to de liver the performance bene ts of parallel le systems to parallel applications In this pa...