A novel photonics-based RF reception approach is proposed as a competitive solution to meet the current challenges of approaches and realize high performances at same time. The adopts superheterodyne configuration by combination manner electronic techniques photonic techniques, including ultra-wideband generation optical LO, two-stage frequency conversion real-time IF compensation. An engineeri...

This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAIADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficien...

incoming RF signals to suppress a certain diffraction modes. The set of experimental verifications with two type AO modulators operating in Raman-Nath (hard flint cell) and Bragg (TeO2 cell) regimes have been performed. With use of the analogue third order polynomial RF synthesizer [2] there were obtained a rather good suppression of two-tone second-order intermodulations in space of the second...

The cognitive radio wireless sensor network (CR-WSN) is experiencing more and more attention for its capacity to automatically extract broadband instantaneous radio environment information. Obtaining sufficient linearity and spurious-free dynamic range (SFDR) is a significant premise of guaranteeing sensing performance which, however, usually suffers from the nonlinear distortion coming from th...

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q2 Random Walk switching scheme. The interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage noise shaper reduces the effective pha...

The high-speed analog-to-digital converters (ADC) that convert an analog signal voltages into binary coded signals at sampling rates greater than 1 Msample/s have been in fast development and are being widely used in many advanced systems in communications, measurements and image processes. These systems are continuously creating a great demand on the speed and resolution of the ADCs to improve...

In this paper, the design requirements of different mixers for direct conversion receivers are discussed. Special attention has been paid into the detection of amplitude-modulated RF signal envelope. Three active mixers have been implemented to investigate the discussed requirements by using a 0.35-μm, 25-GHz BiCMOS technology. The same process allows an objective comparison between the differe...

A dual-drive LiNbO(3) architecture modulator with chirp management is proposed and developed offering SFDR > 25 dB in a 1.4 V bias excursion compared to only 0.5 V bias excursion in a conventional Mach-Zehnder electro-optical modulator (MZ-EOM). The architecture effectively extends the linear regime and enables the optical transmission of wireless systems employing orthogonal division multiplex...

This paper presents a novel low-power 6-bit ADC architecture for Bluetooth transceivers. It utilizes sequentially staged 3-bit integrating converters with interleaved sample and hold circuits. The characteristics of this architecture as well as areas that could lead to even more efficient devices are discussed. The device consumes 5.88mA of current, 14.7mW of power at a sampling rate of 50 MSam...

In the 1950s and 1960s, dc performance specifications such as integral nonlinearity, differential nonlinearity, monotonicity, no missing codes, gain error, offset error, and drift, etc., were primarily used to characterize data converters. These specifications were adequate during this era, because most early applications (with the exception of PCM and radar, for example) dealt with dc or low f...