It is generally desirable to complete design tasks in parallel in order to reduce the overall development time. However, completing tasks in parallel may sometimes increase the total amount of rework that must be done, thereby increasing the total engineering effort, the development cost and the lead time. The technique described in this paper helps to decide between serial and parallel schedul...

Optical packet compression/expansion allows an ultra-fast media access in packet-switched optical networks. A novel optical packet rate-conversion scheme enabling simultaneous compression/expansion and serial-to-parallel conversion of large optical packets is proposed and investigated. Thereby the rate-conversion time is reduced.

Abstract A new approach to optimize a configurable twodimensional (2-D) linear feedback shift registers (LFSR) for both embedded and random test pattern generation in built-in self-test (BIST) is proposed. This configurable 2-D LFSR based test pattern generator generates: 1) a deterministic sequence of test patterns for random-pattern-resistant faults, and then 2) random patterns for random-pat...

A parallel architecture of a parser for Natural Language is described. A serial architecture has been already realized 6] and is currently used in the Process Grammar Development Environment (PGDE) 8], a system for the construction and testing of Natural Language grammars and the generation of the corresponding parsers. The PGDE is built around the Process Grammar Processor (PGP) running a mode...

In this paper we present a new representation of the AES key schedule, with some implications to security AES-based schemes. particular, show that AES-128 schedule can be split into four independent parallel computations operating on 32 bits chunks, up linear transformation. Surprisingly, property has not been described in literature after more than 20 years analysis AES. We two consequences ou...

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor family. AQFP gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement energy-efficient switching process, adiabatic switching. We have proposed a low-latency scheme, delay-line clocking, demonstrated basic gates. In order test more complex circuits, serializer/deseria...

the large amount of computation necessary for obtaining time optimal solution for moving a manipulator on specified path has made it impossible to introduce an on line time optimal control algorithm. most of this computational burden is due to calculation of switching points. in this paper a learning algorithm is proposed for finding the switching points. the method, which can be used for both ...

In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N -bit buffer whose accumulated codelength is at most N . The proposed method partially breaks the recursive dependency related to the MPEG-2 VLD. All possible codewords in the buffer are detected in parallel and the sum of the codelengths is provided to the e...

This paper discusses ways of determining whether the human parser is serial maintaining at most, one structural interpretation at each parse state, or whether it is parallel, maintaining more than one structural interpretation in at least some circumstances. We make four points. The first two counterclaims made by Lewis (2000): (1) that the availability of alternative structures should not vary...