This paper shows that not every scan cell contributes equally to the power consumption during scan based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells. Hence the transitions at these scan cells have a larger impact on the power consumption during test application. These scan cells are called power s...

We implement a test pattern generation algorithm for synchronous sequential circuits. The sequential test generation algorithm, which is effective for small and medium sized sequential circuits, is based on the PODEM algorithm. In this paper we first implement the standard PODEM algorithm using C++ which is fully tested using combinational circuits. Then we generate test patterns for sequential...

This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information an...

Sequential optimization techniques fall in two broad categories: state-based and structure-based [4]. Structurebased techniques optimize a circuit netlist by interleaving retiming and combinational synthesis in different ways to improve design metrics such as delay, area, and power. Examples of such optimizations include among others: peripheral retiming [7], architectural retiming [6], and ite...

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...

We revisit the long-neglected problem of sequential circuit constructions from regular expressions. The class of languages that are recognized by sequential circuits is equivalent to the class of regular languages. This fact is shown in [5] together with an inductive construction technique from regular expressions. In this note, we present an alternative algorithm, called the trigger-set approa...

Testing for intermittent faults in digital circuits has been given significant attention in the past few years. However, very little theoretical work was done regarding their detection in sequential circuits. This paper shows that the testing properties of intermittent faults in sequential circuits can be studied by means of a probabilistic automaton. The evaluation and derivation of optimal in...

In this paper, we address the problem of verifying the equivalence of two sequential circuits. A hybrid approach that combines the advantages of BDD-based and ATPG-based approaches is introduced. Furthermore, we incorporate a technique called partial justification to explore the sequential similarity between the two circuits under verification to speed up the verification process. Compared with...

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q ). This paper presents an innovative ternary D Flip-Flap...

Complex VLSI circuits impose constraints on a test generator which are very diicult to handle using deterministic algorithms. Thus, a major goal in developing a new test generator is to have the capability of handling constraints, but without sacriicing the performance and eeectiveness of deterministic approaches. In this paper, we describe a hybrid sequential circuit test generator which combi...