This paper analyzes the main factors limiting bandwidth expansion of low-noise amplifiers (LNA) and designs a broadband LNA with 2-40.5 GHz. The is designed using multiple methods, including cascode, resistance feedback, cascode Darlington amplifier. amplitude-frequency characteristics principle three structures are studied theoretically based on small-signal equivalent circuit model. Thanks to...

In this paper presents a optimization of linearity of low noise amplifier by using post linearization techniques. in this technique we have used diode connected mosfet as IMD sinker also used interstage matching for gain enhancement and reducing the effect of nonlinearity in common gate stage of cascode amplifier, this has done by using UMC .18um CMOS Technology in cadence tool. We got gain 14d...

In this paper, two fully-differential low noise amplifiers based on classical cascode topologies are presented. The first one is enhanced with noise canceling technique and the second one is based on a negative feedback stage. These circuits have been designed to fulfill the lower band of SKA requirements with a 1.5 GHz bandwidth below 2 GHz. Both chips have been implemented using NXP QUBIC4G S...

A multi-output second generation current conveyor (MOCCII), that can be used to realized first, second and third generations current conveyors, is proposed. The MOCCII consists of a CMOS differential stage for the voltage input, push-pull stage and the improved cascode current mirrors for the current output. Feedback techniques are proposed in order to provide a voltage gain of 0.991, a current...

Abstract: A CMOS LNA using MEMS Technology. Highlighting the "on-chip" inductors with quality factor used to replace previous off chip models. The operating frequency fo=2.4GHz with power dissipation of 20mW and overall noise figure of less than 1dB . It achieves an input return loss S11=-37.7dB. With a supply voltage of Vdd=2.7V giving out S21=24.3dB, S12= 40.7dB, and S22=-30dB. Cascode topolo...

We report traveling-wave amplifiers having 1–112 GHz bandwidth with 7 dB gain, and 1–157 GHz bandwidth with 5 dB gain. A third amplifier exhibited 5 dB gain and a 180GHz high-frequency cutoff. The amplifiers were fabricated in a 0.1m gate length InGaAs/InAlAs HEMT MIMIC technology. The use of gate-line capacitive-division, cascode gain cells and low-loss elevated coplanar waveguide lines have y...

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low power applications is presented in this review. The topics discussed include subthreshold operation in FET devices, micro-currentmirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transcond...

This paper presents a new compensation method for fully differential two-stage CMOS operational transconductance amplifiers (OTAs). It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for minimum settling time of the proposed compensation technique for a two-stage class A/AB OTA is described. To demonstrate ...

The design of a two-stage differential cascode power amplifier (PA) for 81-86 GHz E-band applications is presented. The PA was realised in SiGe technology with fT/fmax 170/250 GHz. A broadband transformer with efficiency higher than 79.4% from 71 GHz to 96 GHz is used as a BALUN. The PA delivers a 4.5 dBm saturated output power and exhibits a 13.4 dB gain at 83.6 GHz. The input and output retur...

Introduction p1 1 Background p2 a) The EKV MOS Model Formulation and Usage p2 b) The Switched Current Memory Cell Principle p4 2 Tips on selecting simulator parameters for a discrete-time simulation p6 3 Example 1Regulated Cascode Memory Cell (saturated) p6 4 Example 2 SI track-and-hold cell, weak/moderate inversion p8 5 Issues on higher-level modeling p11 6 Conclusions p11 7 References p11