This paper presents preliminary data on the transfer and output characteristics of a GeOXcladded Ge quantum dot (QD) gate Si MOSFET. The MOSFET is formed by depositing cladded QDs above the SiO2 gate insulator formed on pSi region, sandwiched between n-type source and drain. Ge (~ 2 to 8 nm) nanoparticles, cladded with GeOX (~1nm) layers, are deposited using site-specific self-assembly. In addi...

Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 μm Technology. Floating gate MOSFET have low power Dissipation hence it is an attractive solution in design of data converters, low voltage op -amp with rail-to-rail input and...

The structural and optical properties of Ge quantum dots (QDs) grown on Si(001) for mid-infrared photodetector and Ge nanocrystals embedded in oxide matrices for floating gate memory devices are presented. The infrared photoluminescence (PL) signal from Ge islands has been studied at a low temperature. The temperature- and bias-dependent photocurrent spectra of a capped Si/SiGe/Si(001) QDs infr...

In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed sub-threshold transient comp...

Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assum...

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6m CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a la...

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in:...

Dynamic Threshold (DTMOS) circuits have been proposed as a circuit style for low-power VLSI systems that takes advantage of the independent body control in partially-depleted SOI. As SOI technologies have scaled, the increasing body capacitance and body resistance have limited the effectiveness of DTMOS circuits that drive the body at the same speed as the gate. An analysis of DTMOS in 0.13μm P...

Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic to the amplifier (thennal noise, Ilfnoise). As integrated drcuit design moves increasingly towards mixed signal implementations, the design of low-noise analog amplifiers must be re...evaluated to consider the switching noise generated by on-<:hip digital circuitry. We designed three fully differential ver...

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantile...