Decoupled computer architectures provide high scalar performance by exploiting the ne{grained parallelism existing between the access and execute functions in a computer program. These architectures employ an access processor to perform data fetch ahead of demand by the execute process. Some of the decoupled archi-tectures employ identical access and execute processors, but special processors t...

This paper describes the development on RASSP Benchmark 1 and 2 of the synthetic aperture radar (SAR) image processor using the RASSP design environment. The overall process flow developed by Lockheed Martin’s Advanced Technology Laboratories, as applied on the SAR processor, is illustrated. Results from using executable specifications; parametric cost estimating tools and VHDL-based performanc...

In this paper we consider an optimization problem that arises in the execution of parallel programs on shared-memory multiple-instruction-stream, multiple-data-stream (MIMD) computers. A program on such machines consists of many sequential program segments, each executed by a single processor. These segments interact as they access shared variables. Access to memory is asynchronous, and memory ...

The single communication channel is shared by all the processors for Inter-Processor Communication (IPC) in a distributed system. A program whose execution is distributed among several processors in a distributed system has the total processing cost equal to the sum of Execution Costs (EC) and Inter-Processor Communication, which are function of the amount of data transmitted. An optimal assign...

Embedded software continues to play an ever increasing role in the design of complex embedded applications. In part, the elevated level of abstraction provided by a high-level programming paradigm immensely facilitates a short design cycle, fewer design errors, design portability, and Intellectual Property (IP) reuse. In a large class of embedded systems, dynamic multitasking using traditional ...

Run-time data redistribution can enhance algorithm performance in distributed-memory machines. Explicit redistribution of data can be performed between algorithm phases when a diierent data decomposition is expected to deliver increased performance for a subsequent phase of computation. Redistribution, however, represents increased program overhead as algorithm computation is discontinued while...

Reliable object tracking at video speed is a task that requires high performance. We have analyzed the various parts of typical algorithms and found that some parts of program flows are best performed on a parallel platform for performance reasons and other parts are better performed on a sequential processor for reliability and versatility reasons. Combining the two processing profiles in one ...

This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully utilizing the microcode-based control scheme, that is one of the most characterizing features of a CISC processor. The optimization process includes two key techniques, generation of application-specific complex instructio...

Reconngurable logic systems approach the performance of Application-Speciic Integrated Circuits (ASICs) while retaining much of the generality of conventional computing systems through reconnguration. Unfortunately, the development of these systems, unlike conventional software systems, is hardware intensive , requiring signiicant hardware development time. One way to introduce a more exible de...

— This paper presents a new design for parallel solid voxelization using the multi-processor pipeline by slicing the program by forced interrupts. The proposed system provides a simple and effective solution to the on-the-fly parallel solid voxelization by relocating the portions of incoming data from processor to processor. It does not need conventional complicated parallel computing methods, ...