Dynamic Threshold (DTMOS) circuits have been proposed as a circuit style for low-power VLSI systems that takes advantage of the independent body control in partially-depleted SOI. As SOI technologies have scaled, the increasing body capacitance and body resistance have limited the effectiveness of DTMOS circuits that drive the body at the same speed as the gate. An analysis of DTMOS in 0.13μm P...

Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approx...

-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied implement cyclic-coupled oscillator (CCRO). Compared an inverter-based CCRO with multi-drive injection, eliminates static short-circuit current drawn from supply when drive circuits are conflicting logic states, thus reducing power c...

The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These differen...

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

Carbon nanotube field effect transistors (CNFETs) are being extensively studied as possible successors to Silicon MOSFETs. Implementable CNTFET circuits have operational characteristics to approach the advantage of using MVL in voltage mode. In this paper we used CNTFETs to implement the improved Gödel basic operators. This paper presents arithmetic operations, implication and multiplication in...

A new dynamic differential logic family, Short-Circuit Current Logic (SCL), is proposed for low-power high-performance applications. It achieves low-power consumption by using an aggressively reduced logic swing without requiring restoration circuitry. Using a 0.35μm CMOS technology and a nominal supply voltage of 3.3V, a SCL full-adder 8 carry ripple adder (CRA) is implemented. It offers an or...

this paper proposes a novel robust control scheme based on delay-dependent h∞for unified power quality conditioner (upqc) in a microgrid under the influence of the delay and parameter uncertainties. a new upqc model considering the effects of the delay and parameter uncertainties is established. then, the h∞ controller is designed based on the cone complementarity linearization (ccl) algorithm....

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been inve...