| This paper presents a salient method to nd an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. F...

Precision microwave measurement systems require highly stable oscillators with both excellent long-term and short-term stability. Compared to components used in laboratory instruments, dielectric resonator (DRO) offer low phase noise greatly reduced mechanical complexity. To further enhance performance, phase-locked loop (PLL) stabilization can be eliminate drift provide precise frequency contr...

In this paper we study and present some results on the performances of frequency tracking for Ka-band satellite communications in rain fading channels. The carrier frequency is tracked using a 2 order hyperbolic phase detector based digital-phase locked loop (D-PLL). The hyperbolic D-PLL has the capability of extending the tracking range compared to the other D-PLL and hence can be designed suc...

A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS pr...

In this paper we describe a novel Phase-Locked Loop (PLL) design for clock management applications. Such PLLs should operate over a wide range of frequencies, have tight constraints on jitter, power consumption and acquisition time, while being dynamically programmable by software means. In addition to the conventional fine tuning loop, the PLL has a coarse tuning loop to control the operating ...

An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to i...

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and gain control. The PLL consisting of phase frequency detector (PFD), filter, voltage-controlled oscillator (VCO) makes the to be locked at resonant frequency. is modeled by Butterworth–Van Dyke equivalent model motional resistance 72.8 kΩ, 6.19 fF, i...

—For positioning with Global Navigation Satellite System (GNSS) in urban canyon area, besides the weak signal power, the satellite signal may also be frequently sheltered and no power can be received. It is a great challenge for the GNSS receiver to keep positioning continuously. If the tracking loop in GNSS receivers can recover locking the signal soon after the signal appears again, it will ...

The All-Digital Phase-Locked Loop has several advantages when compared with traditional charge-pump based PLL. We will introduce some of its advantages in this paper, showing how they can be used to improve the system’s performance. In addition, performance limitations of the system will be discussed.