Composite Galois Field GF ((2)) multiplications denote the multiplication with extension field over the ground field GF (2), that are used in cryptography and error correcting codes. In this paper, composite versatile and vector GF ((2)) multipliers are proposed. The proposed versatile GF ((2)) multiplier design is used to perform the GF ((2)) multiplication, where 2 ≤ x ≤ m. The proposed vecto...

A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...

This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that uses a novel BCD–4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. Decimal floating-point multiplication is important...

<p><span>The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with features added advantage performing complex algorithms high-performance computations. This manuscript implements an efficient arithmetic (RFPA) unit, and its performance metrics realized detail. RFP adder/subtractor (A/S), multiplier, divider...

This contribution describes a new class of arithmetic architectures for Galois fields GF (2k). The main applications of the architecture are public-key systems which are based on the discrete logarithm problem for elliptic curves. The architectures use a representation of the field GF (2k) as GF ((2n)m), where k = n · m. The approach explores bit parallel arithmetic in the subfield GF (2n), and...

An exceptional moduli set Residue Number System (RNS) of high element go (DR) can accelerate the execution of very large word-length tedious increases found in applications like open key cryptography. The modulo 2-1 multiplier is normally the noncritical data path among all modulo multipliers in such high-DR RNS multiplier. This planning slack can be abused to diminish the framework region and ...

We study Dickson bases for binary field representation. Such representation seems interesting when no optimal normal basis exists for the field. We express the product of two elements as Toeplitz or Hankel matrix vector product. This provides a parallel multiplier which is subquadratic in space and logarithmic in time.

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi cantly reduced by a technique known as truncated multiplication. With this technique, the least ...