نتایج جستجو برای: optical network on chip

تعداد نتایج: 8822997  

2003
Bart Vermeulen John Dielissen

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips’ ÆTHEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and tes...

2003
Bart Vermeulen John Dielissen Kees Goossens Calin Ciordas

In this article we present test and verification challenges for system chips that utilise on-chip networks. These systems on a chip (SOCs) and networks on a chip (NOCs) are introduced, where the NOC is exemplified by Philips’s ÆTHEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using a NOC both for testing and ver...

2004
Julien Schmaltz Dominique Borrione

We present a functional approach, based on the ACL2 logic, for the specification of system on a chip communication architectures. Our decomposition of the communications allows the method to be modular for both system definition and validation. When performed in the context of the ACL2 logic, all the definitions and theorems are not only reusable, but also constitute an executable and proven va...

2008
Hans G. Kerkhoff Oscar J. Kuiken Xiao Zhang

Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitati...

2016
Vincenzo Rana Marco Domenico Santambrogio Simone Corbetta

In traditional System-on-Chip design it is possible to know in advance the actual communication requirements, the application needs and all the components (modules) needed to realize the desired architecture. They can be understood a priori, at synthesis-time by the analysis of the application specification. For this reason, once all the components of the system have been defined, they will rem...

Journal: :IJERTCS 2010
Sanna Määttä Leandro Möller Leandro Soares Indrusiak Luciano Ost Manfred Glesner Jari Nurmi Fernando Gehm Moraes

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on th...

Journal: :J. UCS 2012
Maurizio Palesi Rafael Tornero Juan M. Orduña Vincenzo Catania Daniela Panno

Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integration. The advancement of manufacturing technologies in terms of integration leads us to SoCs with many (e.g., 10–1000) digital units (e.g., processor cores, controllers, storage, application-specific units) that need to be interconnected in an efficient and reliable way. The Network-on-Chip (NoC...

2012
Deepika Pandey Kamlesh Gupta

System-on-Chip (SOC) is a microchip consisting of different components such as processor, memory and logic circuitry all on the same chip and for providing communication between these components on the chip Network-on-Chip (NOC) is required as the conventional interconnects are not suitable to fulfil the demands. The application of traditional network technologies in the form of Network-on-Chip...

2005
M. Amde

Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g....

2013
Mridula Agarwal Rupesh Dubey Nitin Jain Deepak Raghuvanshi

As the integration density and complexity of the system-on-Chip (SOC) increases, the conventional interconnects are not suitable to fulfil the demands. The application of traditional network technologies in the form of Network-on-Chip is a possible solution. NoC design space has numerous variables. As an improved topology is selected complexities decrease and power-efficiency increases. In this...

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