Two back-to-back half day workshops on complementary but synergistic topics DDDAS/Infosymbiotics Applications and DDDAS/Infosymbiotics Software and Infrastructure have been organized for HiPC 2015 to be held on Day 1 of the conference. Workshop 3 to be held in the morning will cover InfoSymbiotics/Dynamic Data Driven Applications Systems (DDDAS) for Smarter Systems; Workshop 4 in the afternoon ...

Dr. Dimitris Vasiliadis is currently head of the Network Operations Center (NOC) of Technological Educational Institute (T.E.I.) of Epirus, a node of the Greek Research and Technology Network (GRNET). He has published more than 30 papers. He has been a PC member and referee in various international journals and conferences. His research interests include Performance Analysis of Networking and C...

This document considers the challenges to obtain competitive silicon technology for the upcoming generation of SystemOn-Chip ICs. It suggests planar fully depleted technology deserves serious interest. After outlining some implementation choices, a number of circuit-level benchmark results as well as some important design aspects are presented. It is found that this technology combines high per...

In this paper we present a flexible performance estimation tool calledNessie developed toprovide system-on-chip designerswith automated multi-objective design space exploration and its related tool called Yeti building and executing reusable closed-formed models. After reviewing the existing closed-formed expressions based and application/platform mapping performance estimation tools, we propos...

A sensor network is made up of numerous small independent sensor nodes with sensing, processing and communicating capabilities. The sensor nodes have limited battery and a minimal amount of on-board computing power. This paper presents a novel methodology that utilizes source and path redundancy technique to effectively reduce the required energy consumption while at the same time maximize the ...

Platforms consisting of many computing cores have become the mainstream in high performance computing, general purposecomputing and, lately, embedded systems. Such systems provide increased processing power and system availability, but often impose latencies and contention for memory accesses as multiple cores try to reference data at the same time. This may result in sub-optimal performance un...

This paper reports performances of improved Liquid Dielectrophoresis (LDEP) devices made of Al2O3, HfO2 or ZrO2 as dielectric layers, rather than using classical dielectric layers (SiN, SU-8 resin, SiO2...). These layers have been evaluated on several parameters, such as the threshold actuation voltage, the resistance to the electric field and the droplet generation process. The High-K material...

This study set out to explore the impact of three levels of task planning on the accuracy of task-based oral performance with narrative task types among sixty Iranian sophomores majoring in Teaching English as a Foreign Language (TEFL) at Islamic Azad University – Tabriz Branch. It was hypothesized that simultaneous pre-task/on-line planning would lead to more accurate performance. To test the ...

Over the past decade, increasing the number of cores on a single processor has successfully enabled continued improvements of computer performance. Further scaling these designs to tens and hundreds of cores, however, still presents a number of hard problems, such as scalability, power efficiency and effective programming models. A key component of manycore systems is the on-chip network, which...