Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel Architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating system...

Abstract. This paper describes Sunflower, a full-system microarchitectural evaluation environment for embedded computing systems. The environment enables detailed microarchitectural simulation of multiple instances of complete embedded systems, their peripherals, and medium access control / physical layer communication between systems. The environment models the microarchitecture, computation a...

The realization of a high pe@ormance modem microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be pe@ormed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b fourway supersca...

Providing quality mobile video applications in hand-held mobile devices requires increased computational capability. Using Single Instruction Multiple Data (SIMD) techniques to expose and accelerate the data parallelism inherent in video processing increases performance in handheld and wireless systems. The paper introduces a new 64-bit SIMD coprocessor of the Intel©R XScale©R microarchitecture...

This paper discusses early results from a project called Morph where the goal is to develop a microarchitecture that can adapt its intrinsic performance dynamically. By observing that power dissipation is, to a first approximation, proportional to a power of the performance, reducing the performance characteristics thus reduces the power even faster, resulting in greatly improved performance/ w...

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchit...