In recent years, there have been major advances in CMOS VLSI technology, which generated great interest in electronic circuits, which is more efficient by perfection performance and power consumption. Circuits, called multi valued logic circuits offer several potential opportunities for improvement of present vlsi designs. Current mode CMOS multivalued logic circuits are interesting and have ma...

This paper presents a novel modified comparator based on the combination of 2N-2N2P adiabatic logic and two phase adiabatic static clocked logic (2N-2N2P and 2PASCL), combination of efficient charge recovery adiabatic logic and two phase adiabatic static clocked logic (ECRL and 2PASCL). This new structure computes a decision making signal faster than the existing methods. The introduced logic b...

In this paper, a novel method to build under-voltage-lockout (UVLO) circuit has been developed. The method based on bandgap reference voltage comparator, which take advantage of a reference voltage produced by itself realizes voltage compare, stability of parameters such as threshold point voltage, hysteretic range, without utilizing an extra bandgap reference voltage. An abstractive feature of...

Patients receiving placebo do not merely receive an inert substance but also receive support, concern, and reassurance that assists the therapeutic alliance and encourages the positive attitude that forms the basis of cognitive treatment. Response to non-specific factors is seen in all fields of medicine but is particularly potent in psychiatry. The placebo response is variable across settings ...

A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises signif...

Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is design...

The need for low-power and high speed analog-to-digital converters is pushing toward the use of dynamic comparators to maximize speed and power efficiency. In this paper, performances of various types of the dynamic comparators are being compared in terms of speed, delay and power. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional compara...

A new dynamic comparator is presented using modified gain stage followed by latch stage for high speed analog-to-digital converter. The gain stage of proposed comparator is a modified class AB pre-amplifier which makes it suitable for high speed of operation with small delay time and low power. The circuit is simulated in 180 nm process technology using tool Cadence Virtuoso with a supply volta...

The design and performance of a Next Generation Sampling Comparator Probe (NGSCP) is described. It is intended as one of a group of probes designed for use with the NIST Sampling Waveform Analyzer (SWA). The probe design is centered on an application specific integrated circuit (ASIC) analog comparator featuring a bandwidth of 6 GHz. The design considerations of the ASIC analog comparator and t...

Abstract As photonic linear computations are diverse and easy to realize while nonlinear relatively limited difficult, we propose a novel way perform by operations in high-dimensional space, which can achieve many functions different from existing optical methods. practical application, the arbitrary binary between two Boolean signals demonstrated implement programmable logic array. In experime...