---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Double-tail comparator is basically designed for SAR-ADC in order to optimize the power with which the circuit operates on high-speed. The circuit is designed under 90 nm CMOS technology means by reducing the technology the parameters get also redu...

Testing of Sequential circuits can be done by two test vectors (all 1’s and all 0’s) if the circuits were based on the conservative logic. The circuit is made to be tested by designing the circuit with the help of Reversible logic gates. Toffoli gate is used as reversible gate in this paper. Sequential circuits such as latches, flip flops are designed with the help of conservative logic reversi...

Quantum theory of computation establishes that there are problems for which quantum algorithms are far more efficient than their classical counterpart. Advances in quantum computing have initiated the design of systems based on quantum logic gates. Quantum computer hardware being primarily available in research laboratories at present, it mandates the ability to design, develop and test quantum...

The synthesis of digital circuits is generally performed in two level logic switching algebra. But if we increase the representation domain from two level logic (N=2) to N>2 then the design of Multiple Valued Logic (MVL) digital circuits is possible. Interconnections play an important role in deep submicron designs as they affects power and area. Due to the requirement of interconnections the d...

This paper presents a new dual-rail PLA with 2-input logic cells. The 2-input logic cells composed of passtransistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA without degradation of circuit performance. By using the logic cells, some classes of logic function can be implemented in a smaller circuit area, so that a high-speed and low-power operation is also ac...

Abstmet-A novel way of implementing the Leading Zero Detector (LZD) circuit is pmsented. The implementation is b a d on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both logic synthesis and an algorithmic approach. The algorithm...

1991 Abstract A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulllling the system speciication will produce a particular response to a sequence of simulation commands. This style of veriication has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the low-level details of...

This paper presents a low power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage is comprised of the logic function called efficient charge recovery logic (ECRL) gatesand a handshake controller. ECRL gates have negligible leakage power dissipation. By incorporatingpartial charge reuse (PCR) mechanism the energy dissipation required to complete the evalu...

| A new logic family, Diierential Current Switch Logic (DCSL) for implementing clocked CMOS circuits has been developed. DCSL is in principle a clocked diieren-tial cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better perform...

Implementing a quantum computer at the circuit level has emerged as an important field of research recently. An important topic of building a general-purpose quantum computer is to implement classical Boolean logic using quantum gates and devices. Since the Toffoli gate is universal in classical Boolean logic, any classical combinational circuit can be implemented by the straightforward replace...