Silex Microsystems, a pure play MEMS foundry, offers a high density through silicon via technology that enables MEMS designs with significantly reduced form factor. The Through Silicon Via (TSV) process developed by Silex offers sub 50 μm pitch for through wafer connections in up to 600 μm thick substrates. Silex via process enables “all silicon” MEMS designs and true "Wafer Level Packaging" fe...

— With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among memory-to-processor and processor-to-processor become the key technology to enable those technologies. Simultaneously, the scaling of CMOS makes the switching s...

This paper presents a set of interconnect performance estimation models for design planning with consideration of various effective interconnect layout optimization techniques, including optimal wire sizing, simultaneous driver and wire sizing, and simultaneous buffer insertion/sizing and wire sizing. These models are extremely efficient, yet provide high degree of accuracy. They have been test...

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of m...

Centimeter-range high-density optical interconnect between chips is coming into reach with current optical interconnect technology. Many theoretical studies have identified several good reasons why to use such types of interconnect as a replacement of various layers of the traditional electronic interconnect hierarchy. However, the true feasibility and usefulness of optical interconnects can on...

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this ...

Capacitive and inductive crosstalk noises are expected to be more serious in advanced technologies. However, capacitive and inductive crosstalk noises in the future have not been concurrently and sufficiently discussed quantitatively, though capacitive crosstalk noise has been intensively studied solely as a primary factor of interconnect delay variation. This paper quantitatively predicts the ...

For digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For mid-frequency MOS integrated circuits the RC tree methods can predict the delay to within 10 percent of a SPICE simulatio...

Ion of Interconnect data The problem of design data overload for the user is compounded by tools that don’t provide a way to conceptualize the problem, visualize it, or quickly assess whether a potential solution is good or bad—let alone resolve it. Interconnect flow planner enables designers to create intelligent abstractions of critical interfaces and capture interconnect design intent. vario...

For nanotechnology nodes, the feature size is shrunk rapidly, the wire becomes narrow and thin, it leads to high RC parasitic, especially for resistance. The overall system performance are dominated by interconnect rather than device. As such, it is imperative to accurately measure and model interconnect parasitic in order to predict interconnect performance on silicon. Despite many test struct...