This paper presents the complete design methodology of a very low-voltage ∆Σ third-order modulator from highlevel specifications down to layout. Behavioral models taking into account cell non-idealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit d...

As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The purpose of this paper is to present the layout design of...

This paper describes a low cost, quick turnaround capability for generating high performance, random logic LSI and VLSI devices using the Standard Cell approach. This standard cell approach, described below, utilizes a fully automatic layout capability that automatically maximizes the speed of logic paths identified by the user as critical. In spite of the sophistication and size of the automat...