Abstract A differential Low-noise Amplifier (DLNA) using 0.13 μm CMOS technology is presented. The amplifier is optimized for Bluetooth Receiver applications operating in the 2.4 2.5 GHz band. The inductive degeneration topology used in the DLNA provides low noise, high gain and a large IIP3. The differential LNA was added a cascade output stage to the Single-ended source degenerated stage. Sim...

In this paper, a general architecture for analog implementation of MIN/MAX and other rank order circuits is presented. Based on general architecture, proposed MIN/MAX circuits are implemented. The proposed circuits are composed of a differential amplifier with merged n-inputs and a MCSAL circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high reso...

In this paper we present a floating-Gate differential amplifier input stage with tunable gain. The input stage can be used in a differential ultra lowvoltage (ULV) floating gate (FG) transconductance amplifier. Measured data for the subcircuits operating at 0.8V, 0.5V and 0.3V are provided.

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled siliconcontrolled rectifier (SCR), was proposed to protect the differential LNA. The ...

A new linearization technique for a CMOS high frequency mixer will be presented. The reduction of the total harmonic distortion coefficient is achieved by replacing the simple differential amplifier from the basic multiplier circuit with a cross-connection differential amplifier, with the advantage of canceling the third-order harmonic from the output signal expression. The circuit was implemen...

For my final project, I will be constructing a 70V audio amplifier capable of delivering about 200 watts into a network of transformer coupled loudspeakers. My design utilizes a class G (rail switching) output stage for increased efficiency and lessened cooling requirements. The rest of the amplifier circuit is fairly standard: an input differential pair with negative feedback from the amplifie...

Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic to the amplifier (thennal noise, Ilfnoise). As integrated drcuit design moves increasingly towards mixed signal implementations, the design of low-noise analog amplifiers must be re...evaluated to consider the switching noise generated by on-<:hip digital circuitry. We designed three fully differential ver...

The static characterization of the output section of the Arbitrary Waveform Generator (AWG) requires that its output signal must be digitalized by Analog to Digital Converter (ADC) with higher linearity and resolution than the device under test. In the literature, the problem of high resolution acquisition is translated to the simpler problem of low resolution and high sampling frequency acquis...

This paper presents a 60 GHz CMOS I/Q receiver for the high-speed wireless communication system. It consists of low noise amplifier, single-to-differential (S2D) passive mixer, buffer amplifier with generator, and wideband baseband (BBA) stage. The measured conversion gain 51 dB is achieved. bandwidth 300 MHz achieved from 57 to GHz. 90° tandem coupler was implemented signal generation, which h...

Many commercial benchtop impedance analyzers are incapable of acquiring accurate tetrapolar measurements, when large electrode contact impedances present, as in bioimpedance measurements using electrodes with micrometer-sized features. External front-end amplifiers can help overcome this issue and provide high common-mode rejection ratio (CMRR) input impedance. Several discrete component-based ...