This paper describes experiments to determine how the architecture vis-a-vis routing and functional resources affect the ease with which combinational logic designs may be evolved on a field-programmable gate array (FPGA). We compare two chromosome representations with differing levels of connectivity, and show that the amount of routing and functional resource have a marked effect on the succe...

This paper aims at VLSI realization for generation of a new face from textual description. The FASY (FAce SYnthesis) System is a Face Database Retrieval and new Face generation System that is under development. One of its main features is the generation of the requested face when it is not found in the existing database. The new face generation system works in three steps – searching phase, ass...

This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA). The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA. By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are ti...

We are designing and plan to fabricate a 3-dimensional field programmable gate array. The three dimensional technology, developed at Northeastern University, is based on transferred circuits with interconnections between layers of active devices. Interconnections are in metal, and can be placed anywhere on the chip. Our FPGA architecture, called Rothko, extends the Routing and Logic Block (RLB)...

We developed a simple model of an artificial creature equipped with a brain-like control unit. The model was a miniature car loaded with an FPGA (field programmable gate array) to implement its behavior decision-making circuits based on memory-based architecture. In this paper, we demonstrate the learning capabilities of a few of the systems implemented, and consider which of the learning syste...

We present the design-scheme and physical implementation for a Dynamic Adaptive Neural Network Array (DANNA) based upon the work by Schuman and Birdwell [1,2] and using a programmable array of elements constructed with a Field Programmable Gate Array (FPGA). The aim of this paper is to demonstrate how a single programmable neuromorphic element can be designed to support the primary components o...

This paper describes the architecture of a remote low-cost position sensing infrastructure for ubiquitous computing. To reduce the cost, each tracked object carries an inexpensive active tag that emits a modulated near-infrared signal, which is received and decoded by a camera module. Each camera module consists of a CMOS camera connected to a Field Programmable Gate Array (FPGA) and Ethernet c...

Spread Spectrum (SPSP) Communication is the theoretical basis of Direct Sequence Spread Spectrum (DSSS) transceiver technology. Spreading code, modulation, demodulation, carrier synchronization and code synchronization in SPSP communications are the core parts of DSSS transceivers. This paper focuses on the code synchronization problem in SPSP communications. A novel code synchronization algori...

This paper presents an inexpensive and costeffective configurable platform for designing real time video processing and vision systems. The platform is designed around a Field Programmable Gate Array and provides video input and output interfaces. It has been used to implement several different image and video processing systems, namely with the purpose of prototyping and teaching courses in th...

We propose and demonstrate an Ethernet transport system that can support hard real-time traffics with guaranteed throughput and very low jitter performance even in the presence of asynchronous traffics. The superframe structure-based Ethernet system first synchronizes all the nodes in a network by using the IEEE 1588-compliant boundary clock scheme and then reserves the traffic channels for syn...