High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble F...

A charge-based flash analog digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4-bit $'& KDV EHHQ UHDOL]HG ZLWK P GRXEOH SRO\ SURFHVV DQG tested, confirming its linearity over the full range and a conversion speed of 10 Msamples / s. Introduction : The ...

Features • DigitalClarityTM CMOS Imaging Technology • High frame rate • Superior low-light performance • Low dark current • Simple two-wire serial interface • Auto black level calibration • Support for long integration times • 2 x 2 binning • Anti-aliasing function • Anti-eclipse function • Operating modes: snapshot and flash control, high frame rate preview, electronic panning • Programmable c...

A new approach for measuring the INL and DNL of an A/D Converter that uses histogram information is introduced. Unlike most existing algorithms, this method does not require the generation of accurate input signals so offers potential for use in a Built-in Self-Test (BIST) environment. Multiple inputs are presented to the device under test and the histograms obtained at the output are analyzed ...

Recently, FPGA based digitizers have found attractive applications in signal processing for complex detector arrays in nuclear physics [1]. In the fast digitizers, a flash ADC directly samples and stores the PMT output of scintillation detectors. Digital Signal Processing (DSP) techniques are used to extract the energy and timing information of the acquired signal. DSP not only reduces requirem...

Dynamic latched comparators are most used in analog-to-digital converters. In this paper expressions for the calculation of the offset voltage for two most used topologies are derived. These expressions corroborate previously stated results with analytical support as well as providing useful insight for the design of these comparators by analyzing the influence of each transistor pair individua...

Based on a conventional flash architecture a 4-bit GaAs analog to digital (A/D) converter has been designed using OMMIC-Philips GaAs foundry and particularly its commercial enhancement/depletion mode 0.18 μm pHEMT technology process. The ADC operates at 7.5 GHz sampling rate with full power analog input bandwidth from DC to Nyquist frequency. Differential source coupled FET logic (SCFL) was use...

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