We present an analytical performance modeling approach for concurrency control algorithms in the context of Software Transactional Memories (STMs). We consider a realistic execution pattern where each thread alternates the execution of transactional and non-transactional code portions. Our model captures dynamics related to the execution of both (i) transactional read/write memory accesses and ...

Objectives: The aim of this study was to examine the effectiveness of transactional analysis group training in reducing control-oriented behaviors of spouse in marital discords. Methods: This study employed an experimental design with pre-test and post-test and a control group. The population consisted of women having marital disputes who were referred to counseling centers of Shahre-kord in t...

The main approach of this study is to provide solutions to managers, economists, and tax auditors. To have a clearer perspective of the transactional relationships that distress the taxpayer transaction tax also help them to choose the best strategy to improve tax revenue. In this paper the fuzzy Delphi method was used to identify the indicators affecting suspicious bank accounts. The data coll...

We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a small, fully-associative transactional cache at the same level as the L1 cache. We propose an alternative design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of cap...

In this paper, we present a flexible framework for extending a component model with transactions. We first discuss key issues of combining components with transactions, and different approaches to achieve an appropriate level of transactional functionality in components. We distinguish between the explicit and implicit component participation approaches that differ by whether a component implem...

Hybrid transactional memory (HyTM) [3] works in today’s systems, and can use future “best effort” hardware transactional memory (HTM) support to improve performance. Best effort HTM can be substantially simpler than alternative “unbounded” HTM designs being proposed in the literature, so HyTM both supports and encourages an incremental approach to adopting HTM. We introduce Phased Transactional...

Concurrent programming holds the key to fully utilizing the multi-core chips provided by CMPs. However, traditional concurrent programming techniques based on locking mechanisms are hard to code and error-prone. Transactional Programming is an attempt to simplify concurrent programming where transactions are the main concurrent construct. Hardware Transactional Memory systems provide hardware s...

the asia-pacific region generates over half of global economic activity (54.2%) and about 43.7% of global trade, and is the most dynamic region in the global economy. at the core of this is an increasingly dynamic, vibrant and entrepreneurial small-medium sized enterprise sector. advances in information and communications technology, market liberalisation and moves towards closer regional econo...