The Adders are the critical elements in most of the digital circuit designs, including digital signal processors (DSP) and microprocessors. Extensive research has gone into the VLSI implementations of Parallel Prefix Adders which are known for their best performance. The performance of Parallel Prefix Adders is directly affected by the constraints in the logic implementations of Parallel Prefix...

In the design of Integrated circuits, area plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in many dataprocessing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 4 bit, 8 bit, 16 bit, ...

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dualbit adder design is evaluated and compared vis-à-vis the conventional full add...

Reversible logic has extensive applications in quantum computing, it is a unconventional form of computing where the computational process is reversible, i.e., time-invertible. The main motivation behind the study of this technology is aimed at implementing reversible computing where they offer what is predicted to be the only potential way to improve the energy efficiency of computers beyond v...

The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multipl...

Multiple constant multiplication scheme is the most effective common sub expression sharing technique which is used for implementing the transposed FIR filters. Ripple carry operation allows adder tree to minimize hardware cost, unfortunately it detriment timing and gives low speed operation. To outperform this high speed adder is proposed and analyzed for real time speech signal applications. ...

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these mod...

Abstract -This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme...

In this paper, we performed the comparative analysis of power consumption of array multiplier circuit implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 10 transistorStatic Energy Recovery CMOS adder and 8 transistor CMOS (SERF) circuits. At first, the circuit was simulated with adder modules without applying the SVL circuit. And se...