sheet metal components design and manufacture need a great deal of experience and know-how. strip layout design is usually done with trial and error until best design for strip layout is finally achieved. knowledge for the system is formulated from plasticity theories, experimental results, and the empirical knowledge of field experts. in this paper, an algorithm which can automatically design ...

Purpose In recent years construction projects have become more complex and time-driven, especially with the rapid rise in the number of active partners involved in each project. Space is regarded as a limited resource on construction sites. Proper planning for site layouts ensuring construction activities can be executed safely and efficiently is until now a time-consuming manual process. Site ...

Genetic Algorithm which is based on the Darwinian principle of natural selection has been successfully applied to Berth allocation problem (BAP), which can decide the ships’ berthing position and berthing time at a container terminal. Considering the service priority, handing time deciding variables, safety clearance, as well as the berths’ physical conditions, a dynamic berth allocation with d...

Both the quality of the results of TEX s formula layout algorithm and the complexity of its description in the TEXbook are hard to beat The algorithm is verbally described as an imperative program with very complex control ow and complicated manipulations of the data structures representing formulae In a forthcoming textbook we describe TEX s formula layout algorithm as a functional program tra...

Due to the lack of technology, post-evaluation system spatial syntax has limitations inexperience, 3D vision and problems prediction. The paper focuses on: (1) combined with layout evaluation case Nanning No.2 Middle School, application dynamic in process is refined, rationality verified; (2) sDNA GIS, a isovist model built expand 3D; (3) simulation integrated into solve problem feedback space,...

Transmission-gate conditional-sum (TGCS) adders have been realized in a standard 2.5-pm CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32-bit addition) and consume only moderate chip area (i.e., 80x460 pm2 for 1 bit in a 32-bit adder). They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity a...

Document Image Retrieval! !! G. Pirlo , M. Chimienti, M. Dassisti, D. Impedovo, A. Galiano !!!!!!! Abstract. This paper presents new system for document image retrieval, based on layout-analysis. The system, that is well suited for commercial form retrieval, uses Radon Transform for layout description and Dynamic Time Warping for document image matching. The experimental results, that were cond...

A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permuting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking tinung requir...