Abstract The discovery of ferroelectricity in the fluorite structure based hafnium oxide (HfO 2 ) material sparked major efforts for reviving ferroelectric field effect transistor (FeFET) memory concept. A Novel metal-ferroelectric-metal-ferroelectric-insulator-semiconductor (MFMFIS) FeFET is reported on dual integration as an MFM and MFIS a single gate stack using Si-doped Hafnium (HSO) (FE) m...

In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel field effect transistors (DL-DG-TFETs) with Si0.5Ge0.5 and Si as source material. The CP methodology resolves the issues of random doping fluctuation activation. analog RF performance has been investigated for both proposed devices i.e. DL-DG-TFET Si-source in terms drive current, ...

Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alt...

Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel...

A novel design method of asynchronous domino logic pipeline, which focuses on improving the circuit efficiency and making asynchronous domino logic pipeline design more practical for a wide range of applications. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical ...

A model of a kinematic system consisting of moveable tiles in a two dimensional discrete space environment is presented. Neighbouring tiles repel one another, some tiles are fixed in place. A dual-rail logic gate is constructed in this system.

Abstract In this paper the I-V conduction mechanism for gate injection (-Vg), Stress-Induced Leakage Current(SILC) characteristics and time-to-breakdown(tbd) of PMOS capacitors with p poly-Si and poly-SiGe gate material on 5.6,4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling(MCT) from the gate is proposed for the IV and SILC characteristics at –Vg of our d...

The article reports the extraction of DC characteristics and small signal parameters Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. device is examined analysing: (1) impact presence interface trap charges, (2) temperature variation (200- 400 K). In analysis it has been observed that in case absence charges increase ...

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that ...

This paper proposes a new non-volatile semiconductor memory which features a suspended gate integrated with silicon nanocrystals dots as a floating gate and the MOSFET as a readout. Performing three-dimensional finite element simulations combined with an analytical plate-capacitor model, we clarify the pull-in/pull-out operation of the suspended gate. We also show the dependence of the hysteres...