In the past two years, several multiple data path and pipelined digital signal processors have been introduced to the marketplace. This new generation of DSPs takes advantage of higher levels of integration than were available for their predecessors. It also incorporates multiple execution units on a single core as well as deep execution pipelines. For an introduction to recent trends in DSPs s...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

In 2009, Berkeley Design Technology Inc. (BDTI), an independent benchmarking and analysis firm, launched the BDTI High-Level Synthesis Tool Certification ProgramTM to evaluate high-level synthesis tools for FPGAs. Such tools take as their input a high-level representation of an application (written in C or MATLAB, for example) and generate a register-transfer-level (RTL) implementation for an F...

To satisfy various requirement of embedded video encoder, an embedded video coding system based on TMS320C64xx DSP is designed in this paper. TMS320C64xx DSP (Digital signal processor) is the core of the coding hardware system, and FPGA (Field program gate array) as the co-processor of DSP, which can convert video data into the specified format. For real-time application, we optimize the encode...

AE (Acoustic Emission) testing is an important way in the NDT (Non Destructive Testing) field and wavelet analysis is demonstrated to be a promising method to process AE signal. A wavelet analysis module based on DSP (Digital Signal Processor) implementation is developed for AE testing system of the composite material to make the wavelet analysis system much more small and portable. The impleme...

VHDL synthesis and FPL implementation of a RNS-enabled RISC DSP are presented in this paper. Four parallel modular arithmetic units optimized for multiply-and-accumulate are used in a parallel SIMD architecture. The moduli 256, 251, 241 and 239 are selected to optimize area and performance. Thus, pipelined Galois Field multipliers are used for prime moduli while conventional adders and multipli...

CADRE (Configurable Asynchronous Dsp for Reduced Energy) is a low-power asynchronous DSP (digital signal processor) architecture intended for digital mobile phone chipsets. Central to the architecture are the X and Y register banks, which supply the four processing units with the data they require and to which results are written. The register banks each require 10 read and 6 write ports to ser...

A digital signal processor (DSP), which is a special-purpose microprocessor, is designed to achieve higher performance on DSP applications. Because most DSP applications contain many nested loops and permit a very high degree of parallelism, the DSP multiprocessor has a suitable architecture to execute these applications. Unfortunately, conventional scheduling methods used on DSP multiprocessor...

In order to accurately analyze the dynamic characteristics of the vacuum circuit breaker, a dual-core master-slave processor structure for online monitoring system based on DSP and ARM is proposed. This structure consists of host computer, lower computer and signal processing modules. The lower computer uses DSP as the core, which completes acquisition and data preprocessing of circuit breaker’...

Design and development of real-time, memory and processor hungry digital signal processing systems have for decades been accomplished on general-purpose microprocessors. Various attempts to improve the performance of these systems resulted in the use of dedicated digital signal processing devices like DSP processors and the former heavyweight champion of electronics design — Application Specifi...