نتایج جستجو برای: double gate
تعداد نتایج: 282107 فیلتر نتایج به سال:
In this paper, design of analog circuit using double gate (DG) MOSFET where the front gate output is changed by control voltage on the back gate. The DG devices can be used to improve the performance and reduce the power dissipation when the front gate and back gate both are independently controlled. The analysis of the analog circuits such as CMOS amplifier pair, Schmitt trigger circuit and op...
Reversible logic is one of the emerging technologies having promising applications in quantum computing. This project will deal with the design of a 16 bit reversible Arithmetic Logic Unit (ALU) with 15 operations is presented by making use of Double Peres gate, Fredkin gate, Toffolli gate, DKG gate and NOT gate. A new VLSI architecture for ALU using reversible logic gates is proposed. ALU is o...
In this paper a novel low power double edge pulse triggered flip flop (FF) design is present. First, the pulse generation control logic by using the NAND function and is removed from the critical path to facilitate a faster discharge operation. A simple two transistor NAND gate design is used to reduce the circuit complexity. Second, a double edge conditional discharging flip flop is used to re...
The integrity and issues related performance associated with scaling Si MOSFET channel length promotes research in new device SOI, double gate and GAA MOSFET. In this paper, we pr novel characteristic of horizontal rectangular gate MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some para...
Double-Gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrödinger simulator with tight-binding Green’s function approach. Then we analyze the effect of parameter variati...
It is shown by TCAD simulations how the gate-induced drain leakage which dominates the OFF-current in 22 nm double-gate and 32 nm single-gate SOI nFETs with high-K gate stacks, can be minimized by proper variations of the junction profiles. Based on a microscopic, non-local model of band-to-band tunneling, transfer characteristics are computed after systematic changes in source/drain doping, bo...
1. Abstract Low-field mobilities for (100) and (110) substrate orientations in single-gate (SG) and double-gate (DG) operation modes are compared. It is argued that for the same gate voltage twice as high carrier concentration in DG ultra-thin body (UTB) SOI as compared to the SG mode leads to a higher relative occupation of primed subband ladder for (100) substrate orientation. Efficient scatt...
We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed “atomistic” drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibra...
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