In green iguanas, the pineal controls the circadian rhythm of body temperature but not the rhythm of locomotor activity. As part of a program to investigate the characteristics of this multioscillator circadian system, the authors studied the circadian rhythms of the electroretinographic response (ERG) and asked whether the pineal gland is necessary for the expression of this rhythm. ERGs from ...

Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-lockedloops are widely used as clock generators of microprocessors. Although exploiting advanced circuit techniques reduces the timing jitter induced by the ...

The utilization of cutting planes is a key technique in Integer Linear Programming (ILP). However, cutting planes have seldom been applied in Pseudo-Boolean Optimization (PBO) algorithms derived from the Davis-Logemann-Loveland (DLL) procedure for Propositional Satisfiability (SAT). This paper proposes the utilization of cutting planes in a DLL-style PBO algorithm, which incorporates the most e...

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the ...

Many leading-edge SAT solvers are based on the Davis-Putnam procedure or the Davis-Logemann-Loveland procedure, and thus on unsatisfiable instances they can be viewed as attempting to find refutations by resolution. Therefore, exponential lower bounds on the length of resolution proofs also apply to such solvers. Empirical performance of DLL-based solvers on SAT instances from the pigeonhole an...

in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...

Food waste and loss (FWL), although a growing problem in the world, there is limited research especially from developing country context. In this research, we investigate FWL processing distribution stage of Nigerian Supply Chain (FSC). We propose use Lean Six Sigma (LSS) tools coupled with Double Loop Learning (DLL) to reduce FWL. Using case study strategy explored perception, understanding ex...

An improved architecture for all digital Delay Locked Loop (ADDLL) had been developed and implemented for several applications and design methodologies. In most cases it can be based on standard cells only. Several techniques are used to minimize the jitter, achieving less than 40pS (peak) for 0.13μ technology. The frequency range is very wide, exceeding 500MHz. For 0.13μ core, the area is 0.01...

There exist constants c k > 0, c k ! 0 as k ! 1, such that every DLL algorithm for the satissability of sets of disjunctions of size k using m variables runs for at least (2 m(1?c k)) steps on some inputs. Our proof is based on proving such a lower bound on the tree-like resolution proofs of generalized Tseitin tautologies.