In this paper, we study the computational complexity of commutative determinant polynomial computed by a class set-multilinear circuits which call regular circuits. Regular are with restriction on order in they can compute polynomials. A circuit be seen as analogue ordered defined Hrubes, Wigderson and Yehudayoff [5]. We show that if has small representation sum constantly many circuits, then p...

In the uniform circuit model of computation, the width of a boolean circuit exactly characterises the “space” complexity of the computed function. Looking for a similar relationship in Valiant’s algebraic model of computation, we propose width of an arithmetic circuit as a possible measure of space. We introduce the class VL as an algebraic variant of deterministic log-space L. In the uniform s...

FUNCTION VERIFICATION OF COMBINATIONAL ARITHMETIC CIRCUIT MAY 2015 DUO LIU B.S., JIANGNAN UNIVERSITY, WUXI, JIANGSU, CHINA M.S.E.C.E., UNIVERSITY OF MASSACHUSETTS AMHERST Directed by: Professor Maciej Ciesielski Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for pe...

This paper provides some new lower and upper bounds on computing bilinear forms by arithmetic circuits. The complexity measures considered are circuit size, formula size and time-space trade-offs.

In this thesis we survey the technique of analyzing the partial derivatives of a polynomial to prove lower bounds for restricted classes of arithmetic circuits. The technique is also useful in designing algorithms for learning arithmetic circuits and we study the application of the method of partial derivatives in this setting. We also look at polynomial identity testing and survey an e cient a...

This research addresses system reliability analysis using weakest t-norm based approximate intuitionistic fuzzy arithmetic operations, where failure probabilities of all components are represented by different types of intuitionistic fuzzy numbers. Due to the incomplete, imprecise, vague and conflicting information about the component of system, the present study evaluates the reliability of sy...

The Somos-5 sequence is defined by a0 = a1 = a2 = a3 = a4 = 1 and am = am−1am−4+am−2am−3 am−5 for m ≥ 5. We relate the arithmetic of the Somos-5 sequence to the elliptic curve E : y2 + xy = x3 + x2 − 2x and use properties of Galois representations attached to E to prove the density of primes p dividing some term in the Somos-5 sequence is equal to 5087 10752 .

We present two deterministic algorithms for the arithmetic circuit identity testing problem. The running time of our algorithms is polynomially bounded in s and m, where s is the size of the circuit and m is an upper bound on the number monomials with non-zero coefficients in its standard representation. The running time of our algorithms also has a logarithmic dependence on the degree of the p...

Electrical power systems play a critical role in spacecraft and aircraft. This paper discusses our development of a diagnostic capability for an electrical power system testbed, ADAPT, using probabilistic techniques. In the context of ADAPT, we present two challenges, regarding modelling and real-time performance, often encountered in real-world diagnostic applications. To meet the modelling ch...

Abstract In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic gates. The particular effects captured by the model are: the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model for a compu...