The recent researches on the tracking of binary offset carrier (BOC) modulated signals have been studied focusing on resolving the ambiguity problem caused by the multiple side-peaks in BOC autocorrelation. In this paper, we propose a novel unambiguous BOC tracking scheme with an improved tracking performance by using partial-pulses of BOC signals. Firstly, we observe that a sub-carrier consist...

Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the perform...

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the ...

The implementation of the maximum likelihood estimator for the time-delay estimation problem is practically intractable for navigation signals due to its complexity, especially when due to multipath reception several superimposed replica are taken into account. Recently it has been shown that signal compression techniques can overcome this problem, as the maximum likelihood estimator can be for...

Due to the important relationship between ultrasonic velocity and some properties of sample, the measurement of velocity of ultrasound is widely needed in various fields. In this paper, based on phase-locked loop technique, a new hybrid circuit is designed for ultrasonic velocity measurement and named as UV-PLL. In order to improve the stability of phase and achieve the ability of fast locking,...

A CMOS sub-circuit that is able to improve data communication is described. It removes jitter and hence improves the eye diagram of high-speed digital data signal. The circuit is based on a delay-locked loop and uses a half-frequency reference clock. The prototype circuit is fabricated in 2.5 V, 0.25-μm CMOS and occupies an area of only 270 x 50 μm. It is demonstrated that at 900 Mbit/s NRZ dat...

A fast-locking pulsewidth-controlled clock generator (PWCCG) based on delay locked loop is proposed in this paper. The coarse and fine delay lines and a time-to-digital detector permits the pulsewidth-controlled clock generator (PWCCG) to operate over a wide frequency range. A new dutycycle setting circuit is also presented in this paper that decides the preferred output duty cycle. Result of t...

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using 1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, 2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0...