ii I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. Abstract The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain hi...

Molybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (~2610°C) and low coefficient of thermal expansion (5×10/ oC, at 20 oC) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate re...

INTRODUCTION CMOS Active Pixel Sensors (APS) excel in domains that include low power operation and on-chip integration of analog and digital circuitry. Since these sensors are utilized for applications involving the detection of signals as low as a few electrons, radiation tolerance of such devices is of primary concern. All possible radiation effects are usually grouped into three basic types:...

Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very imp...

The decreasing dimensions of IC devices is rendering the conventional heat diffusion equation highly inaccurate for electrothermal simulations of deep submicron devices. This work integrates the phonon Boltzmann Transport Equation (BTE) in deep sub-micron silicon devices and presents a general methodology for solving the BTE. The approach developed is applicable to both Si bulk and SOI devices ...

CMOS technology has continuously scaled into deep sub-micron regime. With CMOS scaling, many complex design issues arise. The challenges include, but not limited to, the increasing of interconnect delay and power, exponential growth of leakage power, and rapid growth of design complexity. These challenges motivate us to design new CAD algorithms to reduce power consumption (both leakage power a...

On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology , the subthreshold leakage power is becoming the dominant fraction of the total power consumption of those caches. In this paper, we present optimization techniques to reduce the leakage power of on-chip caches assuming that there are multiple threshold voltage...

This tutorial will focus on the emergence of new validation and test issues, factors motivating the emergence of these problems, basic models and the analysis of the underlying electrical phenomena, and several case studies. The primary factors causing a paradigm shift in the area of validation and test that will be discussed are deep sub-micron CMOS technology, high performance system architec...