Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by th...

The use of low-resolution digital-to-analog and analog-to-digital converters (DACs ADCs) significantly benefits energy efficiency (EE) at the cost high quantization noise for massive multiple-input multiple-output (MIMO) systems. This paper considers a precoding optimization problem maximizing EE in quantized downlink MIMO To this end, we jointly optimize an active antenna set, vectors, allocat...

We study collaborative machine learning systems where a massive dataset is distributed across independent workers which compute their local gradient estimates based on own datasets. Workers send through multipath fading multiple access channel with orthogonal frequency division multiplexing to mitigate the selectivity of channel. assume that there no state information (CSI) at workers, and para...

X-ray in situ studies in electrically and laser-heated diamond anvil cells (DACs) at pressures over 80 GPa and temperatures above 2500 K were used to determine stable silica phase at extreme conditions. We demonstrate that so far unidenti®ed phases obtained on the compression of a-cristobalite, new dense silica polymorph in the Martian Shergotty meteorite, and controversial post-stishovite phas...

Battery-powered portable audio devices require low-voltage, low-power, and medium-accuracy digital-to-analog converters (DACs). The proposed structure is inherently suitable for lowvoltage and low-power applications. Fig. 1 shows the block diagram of the complete DAC system. The input of the DAC is a 16-bit serial digital signal DIN; the analog output AOUT drives the headphone load (16Ω paralle...

A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DAC). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) AD...

We provide a rigorous framework for characterizing and numerically evaluating the error probability achievable in uplink downlink of fully digital quantized multiuser multiple-input multiple-output (MIMO) system. assume that system operates over quasi-static channel does not change across finite-length transmitted codewords, only imperfect state information (CSI) is available at base station (B...

The design of Continuous-Time (CT) Sigma-Delta modulator obtained by a discrete-time prototype is discussed. A proper heuristic transformation of the prototype enables an exact equivalence of CT and DT. This permits the trimming by computer simulations of the coefficients of the CT to account for the effect of real analog blocks. Simulation results for a second and third order scheme with real ...

Gradient error can be compensated by optimizing switching sequences of DAC arrays. This paper establishes an absolute lower bound of integral nonlinearity (INL) which may be achieved by optimizing switching sequences. Optimal switching sequences that meet this lower bound are presented for one-dimensional linear gradient error compensation in unary (thermometer decoded) DAC arrays. The sequence...