In this paper, experimental responses of the clamped mild steel, copper, and aluminium circular plates are presented subjected to blast loading. The GMDH-type neural networks (Group Method of Data Handling) are then used for the modelling of the mid-point deflection thickness ratio of the circular plates using those experimental results. The aim of such modelling is to show how the mid-point de...

Abstarct---This paper proposes a new design of highly stable and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 32nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a ...

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and...

The performance limits of carbon nanotube field-effect transistors ~CNTFETs! are examined theoretically by extending a one-dimensional treatment used for silicon metal–oxide– semiconductor field-effect transistors ~MOSFETs!. Compared to ballistic MOSFETs, ballistic CNTFETs show similar I – V characteristics but the channel conductance is quantized. For low-voltage, digital applications, the CNT...

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthr...

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low s...