A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power dissipation has been cut down to a minimum while providing the full output voltage swing at all nodes in the circuit. Furthermore, the complete circuit is implemented with a bare minimum of 28 transistors.

in recent years, with the increasing demand for high-performance portable electronic devices such as laptop cornputers and cellular phones, power dissipation has become a very important performance parameter in VLSI design. One approach to power reduction hvolves the use of circuit topologies different fiom the standard CMOS topology. A probiem with this approach is that there is a lack of desi...

All-spin logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to non-volatility, ultra-low operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale ma...

A fast and energy-efficient multiplier is always needed in electronics industry especially digital signal processing (DSP), image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. Multipliers of various bit-widths are frequently required in VLSI from processors to application ...

This paper describes the architecture, design & simulation of ternary logic gates. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to devices [1]. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of ternary-valued logic circuits have been explored ov...

Asychronous designs have been touted as having potential advantages in average performance, power consumption, modularity, and tolerance of metastability as compared to traditional synchronous logic. While delayinsensitive (DI) asynchronous circuits are theoretically the most desirable type of asynchronous logic because they make the weakest timing assumptions, the complexity of implementing DI...

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal–oxide–semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAM’s), dynamic random access memories (DRAM’s), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting ...

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. Battery operated portable computers and wireless communication products have often been used. Thus low power integrated circuit design has been strongly demanded for implementation. One of the promising techniques of low power design is adiabatic ...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing ...

An Arithmetic logic Unit (ALU) is an integral part of a computer processor. It has the capability of performing a no. of different arithmetic and logic operations such as addition, subtraction, bit-shifts and magnitude comparison. ALUs of various bit-widths are frequently required in very large-scale integrated circuits (VLSI) from processors to application specific integrated circuits (ASICs)....