An important step in today’s Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. To alleviate the growing volume of layout ...

This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in detail. The circuit techniques used to reduce the power dissipation and delay of these components has been explored and the tradeoffs have been explained. The key to low power operation in the SRAM dat...

This paper describes a new manufacturing yield model for submicron VLSI circuits. This model attempts to handle process induced differences between IC layout and actual IC topography. The presented model focuses on the random nature of over and under etching phenomenon. The relevance of the new yield model in submicron domain is analyzed. Examples of yield calculations using the proposed model ...

This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work ha...

The problem of single channel speaker separation, attempts to extract a speech signal uttered by the speaker of interest from a signal containing a mixture of auditory signals. Most algorithms that deal with this problem, are based on masking, where reliable components from the mixed signal spectrogram are inversed to obtain the speech signal from speaker of interest. As of now, most techniques...

The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design complex systems by assembling Intellectual Property components. Latency insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protoc...

The vast majority of IC’s that go into production must reside on a Printed Circuit Board (PCB). Unfortunately, the design and layout of this PCB is often an afterthought and never considered in the planning of the chip itself. The result is a PCB that is very difficult to complete on a minimal number of layers and signal integrity is often compromised. This often creates a huge bottleneck in th...

Given a number of routing layers, the multilayer topological planar routing problem is to choose a maximum (weighted) set of nets so that each net in the set can be topologically routed entirely in one of the given layers without crossing other nets. This problem has important application in the layout design of multilayer IC technology, which has become available recently. In this paper, we pr...

A thermal power station is a power plant in which the prime mover is steam driven. Water is heated, turns into steam and spins a steam turbine which drives an electrical generator. After it passes through the turbine, the steam is condensed in a condenser and recycled to where it was heated; this is known as a Rankine cycle. The greatest variation in the design of thermal power stations is due ...

This paper presents the complete design methodology of a very low-voltage ∆Σ third-order modulator from highlevel specifications down to layout. Behavioral models taking into account cell non-idealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit d...