This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for MEMS. The technique is based on Impulse Response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS). We will demonstrate the use of this technique for an on-chip fast and accurate broadband determination of MEMS behaviour, in particular for the characterisation of MEMS structures such as ...

Reusability is a key factor for the success of the development of low-cost applications. Component-based software engineering (CBSE) aims to address this challenge by providing flexible and easy to use software components. Composability is a key concern of CBSE because software components collaborate with difficulty in spite of the fact that they are known to be compositional. In this paper we ...

This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piece-wise approximation to compute the ideal histogram is developed. These three features allow a ...

In real-time systems, dynamic inconsistencies of software are hardly detected, diagnosed and handled. A built-in test (BIT) method is developed to cope with software dynamic inconsistency. BIT is defined as a new kind of software testing which is explicitly described in object-oriented source code as member functions. BITs can be activated at any designed moment at run-time to detect, diagnose ...

In this chapter we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodologies and algorithms. First, we present a general introduction of terminology, a taxonomy of testing methods and of fault models. Then we discuss the main approaches for the generation of test patterns, both algorithmically and pseudo-randomly, concludin...

In this paper, the authors propose a new transparent built-in self-test method to test in parallel multiple embedded memory arrays with various sizes. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with test interrupts in a real-time manner. The circular scan test interface facilitates the processes of both test pattern generation and signa...

Home networking has been developing rapidly due to the increase of the internet users and the advent of digital economy. In this context, the quality and service under guarantee for internet intelligence electric home appliances has become quite important. Therefore, to guarantee the performance of the appliances, on-line testing for detecting latency faults should be performed. In this paper, ...

3⁄4 In order to accomplish a high speed test on low speed Automatic Test Equipment (ATE), a new instruction based, fully programmable memory, Built-in Self-Test (BIST) is proposed. The proposed memory BIST generates a high speed internal clock signal by multiplying the external low speed clock signal from the ATE. For maximum programmability and small area overhead, the proposed BIST receives t...

This paper proposes a histogram BIST scheme for ADC static testing. This scheme makes use of time decomposition technique and space decomposition technique. The traditional ADC BIST approach based on time decomposition technique can reduce the test hardware overhead, however it will typically produce large testing time. For a monotonic ADC, the output codes have an approximate proportional rela...

We present a new pseudorandom testing algorithm f o r the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed f o r the detection of coulping faults. A s a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.