Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical terms hardware cannot afford to compromise accuracy or reliability. Multiplier, one the most heavily used components, becomes crucial these applications. If optimized, multipliers can impact ...

In VLSI technology, power consumption and delay becomes a major problem in multipliers. To reduce these issues we propose a new multiplier algorithm that combines numerical transformation and shift and add technique. In this design N X N bitmultiplication is done by using successive approximation of (N-1) X (N-1) bit multiplier. The strength of the multiplication is reduced by weight reduction ...

Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed rev...

High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free” floating point arithmetic operations. Floating Point RNS units have obvious advantages over tradition...

In this paper, we have designed a signed booth’s multiplier as well as an unsigned booth’s multiplier for 4 bit, 8 bit and 16 bits performing multiplication on signed and unsigned number. The implementation is done through Verilog on xiling12.4 platform which provide diversity in calculating the various parameters. The unsigned booth multiplication is implemented by doing some modification in t...

This paper presents a new, a highly compact implementation of a 32 32 parallel multiplier based on parallel counters. The new multiplier is designed using the recently proposed Self-Timed Threshold Logic (STTL). The design is based on a direct multiplication scheme using depth 2 (15,4) and (7,3) STTL parallel counters and (4:2) compressors. The proposed parallel multiplier reduces the partial p...