We have developed a compact CMOS motiondetection circuit based on a direction-selective neuralnetwork architecture. The circuit consists of asynchronous current-mode digital subcircuits for edge detection and subthreshold analog subcircuits for motiondetection. SPICE and numerical simulations of the network show that the circuit can successfully extract edge lines from incident images and compu...

The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.

We consider secure multi-party computation in the asynchronous model and present an efficient protocol with optimal resilience. For n parties, up to t < n/3 of them being corrupted, and security parameter κ, a circuit with c gates can be securely computed with communication complexity O(cnκ) bits. In contrast to all previous asynchronous protocols with optimal resilience, our protocol requires ...

Asynchronous circuits have characteristics that differ significantly from thoseof synchronous circuits and, as will be clear from some of the later chaptersin this book, it is possible exploit these characteristics to design circuits withvery interesting performance parameters in terms of their power, performance,electromagnetic emissions (EMI), etc.Asynchronous design is no...

The Balsa synthesis system is presented. Balsa generates purely asynchronous macromodular circuits from CSP-like descriptions similar to those of Philips’ Tangram tool. Balsa targets standardcell and FPGA technologies by producing gate level netlists. Place and route can be performed with existing commercial tools. The DMA controller for the AMULET3i asynchronous microprocessor macrocell is pre...

The paper presents an interactive OSF /Motif-based design framework for high-level specification, analysis and synthesis of asynchronous control c:irc:uits. As novel contributions we propose an object~riented graphical design environment including interfaces to external state of the art asynchronous circuit synthesis tools. The proposed design environment represents a powerful CAE design system...

In this paper we construct a new trace model of delay-insensitive asynchronous circuits inspired by Ebergen’s model in such a way that it satisfies the compositional properties of a category, with additional monoidal structure and further algebraic properties. These properties taken together lay a solid mathematical foundation for a diagrammatic approach to reasoning about asynchronous circuits...

This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today’s computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter ...

A delay-insensitive asynchronous design methodology, named NULL Convention Logic (NCL), is one of mainstream asynchronous design techniques for low-power robust circuit operation. It offers many advantages over synchronous circuit design having scaling issues in nanometer region such as severe process variations, short channel effects, aging effects, and etc. Therefore, this paper proposes a ne...