A new CAD tool used for the interactive exploration of a design space has been developed. The interactive nature of the tool facilitates the acquisition of designer knowledge which may accelerate the development of improved circuit topologies in the future. The tool's cross-platform compatibility and network centric architecture prevents reinvention and facilitates organization-wide or worldwid...

In this paper a universal nth order current-mode filter employing electronically tunable second-generation current conveyors (ECCIIs) and grounded passive elements is proposed. Since the current gain of the ECCII can be controlled electronically by adjusting the ratio of DC bias currents, it is possible to tune all the coefficients of the transfer function independently through the variable cur...

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the ...

In order to solve the problems caused by large dataset, such as the network scale and the training time, a new method of analog circuit fault diagnosis based on distributed neural network is presented in this paper. The model of distributed neural network is simply introduced. The arithmetic mechanism is depicted in detail and the arithmetic description is given. Simulation results show that th...

A CMOS analogue circuit for Gaussian noise generution as well as a novel circuitfor transforming Gaussian noise into uniform noise, hoth.designed/or operating with a supply voltoge o/ I . S K arepresented. Both circuits are optimizedfor U 0 . 3 5 ~ standord CMOS technology using an equation-based design methodology based on generic algorithms. Electrical simulations demonstrate that high noise ...

A rapid yield estimation methodology that aids the analog circuit designer in making design trade-offs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulation, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage op amps, and has been i...

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to d...

In recent years, Defect Oriented Testing (DOT) has been investigated as an alternative testing method for analog circuits. In this paper, we propose a wavelet transform based dynamic supply current (IDD) analysis technique for detecting catastrophic and parametric faults in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously u...

This paper proposes the use of Cellular Non-Linear Networks (CNNs) as physical uncloneable functions (PUFs). We argue that analog circuits offer higher security than existing digital PUFs and that the CNN paradigm allows us to build large, unclonable, and scalable analog PUFs, which still show a stable and repeatable input–output behavior. CNNs are dynamical arrays of locally-interconected cell...

MASC (for Multiple Associative Computing) is a joint control parallel, data parallel model that provides a practical, highly scalable model that naturally supports small to massive parallelism and a wide range of applications. In this paper, we present efficient algorithms for a MASC model with a 2-D mesh to simulate enhanced meshes. Let MASC(n, j) denote a MASC model with n processing elements...