The counter ow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results ow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid p...

This paper describes a case study where a pipeline operator was faced with features in the pipe wall that proved difficult to conclusively identify. An ultrasonic (UT) pig inspection indicated that the pipeline contained numerous deep external defects. However, subsequent excavations indicated that the reported external defects were in fact mainly laminations and/or inclusions. To verify that t...

Extensive research work has been reported on the scheduling of hardware pipelines and software pipelining independently, One interesting problem is how to extend hardware pipeline theory to handle software pipelined loops in user programs. More specifically , the problem is how to maximize the utilization of hardware resources under modulo scheduling for a given II. In this paper, we develop a ...