This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...

Abstract—Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been ...

One of the major challenges associated with the in-mold assembly processes at the mesoscale is the interaction between the polymer melt and the premolded components that are present in the mold. When a high speed, high temperature second stage melt comes in contact with a premolded mesoscale component having similar melting temperatures, the premolded component undergoes thermal softening and p...

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique...

This paper describes dark current characterization of two-stage charge transfer pixels, which enable a global shuttering and kTC noise canceling. The proposed pixel uses pinned diode structures for the photodiode (PD) as well as the storage diode (SD), thereby a very low dark current is expected. In this paper, effects of negative gate biasing and temperature dependency are discussed with devic...

Extensive research is carried-out worldwide to design energy-efficient adiabatic circuits for such biomedical and space applications where conventional energy is limited and speed is not critical. In this paper a new single phase adiabatic or energy recovery logic is proposed and extensively analyzed the energy performance with technology scaling. We present a comparative study among proposed l...

We propose a new global routing area estimation approach for high-performance VLSI and MCMs. The objective is to route nets with minimum density of global cells, producing a two-bend routing for each two-terminal net. A solution to this problem can also be used for quick estimation of necessary wiring space (for standard cell array designs) and diiculty of routing (for gate array designs) in th...

MOBILE networks can be operated in a gate-level pipelined fashion allowing high throught-output. If MOBILE gates are directly chained, a four-phase clock scheme is requiered for this. A single phase scheme is possible adding latches to the MOBILE gates. This paper proposes and experimentally validates a new single-phase interconnection scheme that simplifies the inter-stage element, which trans...