A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simpliied linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used...

This paper introduces a novel architecture for expert systems performing diagnostic problem-solving. The architecture is called \categorization-based" because problems are solved by relating them to relevant categories of known cases using deep knowledge about the application domain. The eeectiveness of the architecture has been validated by an implemented expert system called CHATKB, which doe...

— This paper introduces systolic automata for VLSI as highly concurrent acceptors. Attention is focused on tree automata although other types are also discussed briefly. A number of preliminary results about the capabilities of such automata are obtained. The approach not only opens up a new and interesting area oflanguage theory but also its results give useful hints for VLSI system design par...

In today’s era the demand of Very Large Scale Integrated Circuit (VLSI) is increase due to the growth of the Electronics industry. VLSI has high performance and high functionality at minimum cost and power dissipation. Continuously scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnects delays. The higher power consummation is due to long wiring networks and clock ...

A novel approach and trend on VLSI implementation of a unified framework for hardware supporting of connectionist algorithms is presented in this work. An analog hybrid neural network implemented in VLSI hardware is designed, fabricated, and tested for this purpose.