نتایج جستجو برای: زیرلایه soi
تعداد نتایج: 5227 فیلتر نتایج به سال:
− This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pnjunction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and νMOS circuits. Index Terms −SOI, gated-pn junction, neural logic,
−Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed. Index Terms−Reli...
Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% co...
The concept of matched devices is one of the most important features in analog circuit design, as most analog circuits operation rely on the similarity of electrical behavior of close devices [1]. However, in practice, the characteristics of designed matched transistors are slightly different. Therefore, the design of precise analog circuits requires studies into the matching behavior of device...
Optical data communication is not the only area where silicon photonics will have an impact. Silicon and related group 4 crystals have excellent linear and nonlinear optical properties in the midwave and longwave infrared spectrum [1-6]. These properties, along with silicon’s excellent thermal conductivity and optical damage threshold, open up the possibility for a new class of midwave and long...
We investigated the frequency dependences of Y22 of FDSOI MOSFETs, in which the drain current response delay is observed for the first time. Short channel FD-SOI devices operating in linear region show significant drain current response delay. It is confirmed that FD-SOI MOSFET’s RF behavior can be well reproduced with the proposed model including the drain current response delay.
We propose a design for high quality factor two-dimensional (2D) photonic crystal cavities on silicon-on-insulator (SOI). A quality factor of up to 1.2×10(7) with a modal volume of 2.35(λ/n)(3) is simulated. A very high quality factor of 200,000 is experimentally demonstrated for a 2D cavity fabricated on SOI.
Modeling and performance of on-chip spiral inductors is presented. Y-parameters are obtained from the measured S-parameters of the inductor fabricated in 0.35-μm SOI CMOS technology. Matlab is used to get the π-equivalent circuit model parameters at each frequency point. The SOI CMOS inductor shows better performance characteristics in terms of Q-factor and self-resonance frequency.
confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented.
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