This paper presents a fast and low-power Static Random Access Memory (SRAM) design. SRAM are widely used in computer systems and many portable devices. Proposed SRAM is faster because of precharging at a desired voltage. For the most recent CMOS technologies leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage...

We present a side-channel attack based on remanence decay in volatile memory and show how it can be exploited effectively to launch a non-invasive cloning attack against SRAM PUFs — an important class of PUFs typically proposed as lightweight security primitive with low overhead by using the existing memory of the underlying device. We validate our approach against two SRAM PUF implementations ...

This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRA...

When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...

In this work, the effect of displacement defect (DD) owing to cosmic rays on six-transistor (6T) static random access memory (SRAM) with a 3 nm node nanosheet field-effect transistor (NSFET) is investigated using technology computer-aided design (TCAD) simulation. order comprehensively study uncertainty radiation NSFET 6T SRAM, shape DD cluster cross-section and damaged by in SRAM are considere...

The most research on the power consumption of 6T SRAM has been focused on the static power dissipation and the power dissipated by the leakage current. On the other hand, as the current VLSI technology scaled down, the sub-threshold current increases which further increases the power consumption. In this paper we have proposed 6T (8 X 8) SRAM cells using MCML technology which will reduce the le...

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 500C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the e...

Embedded SRAM is involved in many low-energy applications, e.g. stand-alone wireless sensor nodes. SRAMs have the highest energy contribution in such applications. Unlike dynamic RAM, it does not need to refresh. In modern Trends, the demand for memory has been increases tremendously. We analyze Schmitt-Trigger (ST)-based static random access memory (SRAM) bitcells for ultralow-voltage operatio...

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control wi...

This paper presents the different types of analysis such as noise, voltage, read margin and write margin of Static Random Access Memory (SRAM) cell for high-speed application. The design is based upon the 0.18 μm CMOS process technology. Static Noise Margin (SNM) is the most important parameter for memory design. SNM, which affects both read and write margin, is related to the threshold voltage...