Today's DRAM process is expected to continue scaling, enabling minimum feature sizes below 10nm. To achieve this, the main challenges to address are expected to be refresh, write recovery time (tWR), and variable retention time (VRT) parameters. This paper proposes enhancement features that address these three scaling parameters by simultaneously coarchitecting the controller and DRAM instead o...

Performances of DRAM memories are characterized by memory latency and bandwidth. Contemporary DRAM memories more successfully satisfy demands for higher bandwidth than lower latency. In this paper solutions, which may reduce latency of these memories, are investigated. These solutions are two new controller policies called ’Write-miss Only Close-Page’ and ’Write-miss Only Close-Page-Open previo...

The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple...

This paper discusses an approach to reducing mem ory latency in future systems It focuses on systems where a single chip DRAM processor will not be fea sible even in years e g systems requiring a large memory and or many CPU s In such systems a solu tion needs to be found to DRAM latency and bandwidth as well as to inter chip communication Utilizing the projected advances in chip I O bandwidth ...

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The RAMpage memory hierarchy is an alternative memory organization which addresses the growing CPU-DRAM speed gap, by replacing the lowest-level cache by an SRAM main memory. This paper presents some modifications to the RAMpage hierarchy. More aggressive first level cache implementations are shown to improve performance of the RAMpage model, when context switches were taken on misses to DRAM.

STT-MRAM is one of the most promising non-volatile memory technologies with the potential of becoming a universal memory. However, because of its area, power and latency limitations, STT-MRAM is facing critical bottlenecks in substituting DRAM for main memory. Compared to modern DRAM technology, STT-MRAMs cell area and write power consumption are about four times larger and higher, respectively...

For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M-bit memory chips are now commonplace, and we can expect to see systems shipping in volume with 1 G-bit memory chips within the next two years. Although densities of DRAMs have quadrupled every 3 years, access speed h...

For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M-bit memory chips are now commonplace, and we can expect to see systems shipping in volume with 1 G-bit memory chips within the next two years. Although densities of DRAMs have quadrupled every 3 years, access speed h...

BACKGROUND & AIMS Apoptosis mediated by p53 plays a pathological role in the progression of hepatosteatosis. It is noteworthy that p53 can promote the expression of damage-regulated autophagy modulator (DRAM), an inducer of autophagy-mediated apoptosis. However, the relationship between p53-mediated apoptosis and autophagy in hepatosteatosis remains elusive. This study aimed to examine how p53 ...